1. Technical Field of the Invention
This invention relates generally to Read Only Memory (ROM) and more particularly to a method, apparatus and system for patching ROM code in a digital data processing system.
2. Description of Related Art
As is known, digital data processing systems such as computers, personal media players (e.g., mp3 players), cell phones, and other electronic devices typically use digital data processors, read only memory (ROM), and random access memory (RAM) in their operation. On startup and in operation of a microprocessor, operating code in a ROM is accessed to run operating code. For example, on startup of a personal computer, ROM code is accessed to load initial program instructions, such as boot and initialization instructions.
The way a ROM chip works necessitates the programming of perfect and complete data when the chip is created. By the nature of the ROM structure, it is impossible to reprogram or rewrite a standard ROM chip. For example, if the operating code is incorrect, or the data needs to be updated, the ROM chip must be discarded and replaced with a new chip having replacement code. Creating the original template for a ROM chip is often a laborious process full of trial and error, so replacing or changing merely a single line of ROM code once a template is produced can be a massive undertaking.
There are several reasons for wanting to be able to make changes to ROM code after the ROM is produced. In some cases, electronic products are often developed in short time frames and released without exhaustive testing, therefore ‘bugs’ or defects in the ROM code may be discovered after products have been released on the market. Other circumstances such as a change in operating parameters or conflicting hardware or software may necessitate later alteration of the operating code residing in the ROM. As previously mentioned, it is impractical, laborious and expensive to recall products to manually change the ROM.
With reference to FIG. 1, a known prior art technique of implementing ROM code correction is performed by replacing a piece of ROM-based code with a patch program stored in RAM. FIG. 1 shows a schematic block diagram of a prior-art patch code correcting apparatus. The ROM patch code logic includes eight patch address registers 14 and eight patch address comparators 16. Each patch address register 14 points to a starting location in the ROM code where the program flow is to be changed. The Program Counter (PC) register in a Program Control Unit is compared to each patch address register. When a comparator determines that the address of a fetched instruction is identical to an address stored in one of the patch address registers, the data bus 10 is forced to the corresponding JMP instruction by JMP Target Address Generator 20.
The patch address register 14 contents are compared with the address bus 12 used to initiate the program fetch. When the address in the patch address registers 14 is equal to the contents of one of the patch address registers, a PATCH DETECTED signal 24 is generated that injects a JMP instruction into the data bus 10, replacing the instruction that otherwise would have been fetched from the ROM. The JMP target address is determined according to the identity of the comparator that generated the PATCH DETECTED signal 24. The JMP target can be any one of the predetermined locations in the program memory space stored by RAM 22. The specific target address is mask-programmable. A user may download a piece of patch code to one of the predetermined target locations in RAM 22.
As may be seen from FIG. 1, the prior art ROM patch code scheme requires a comparator for each block of patch code that is provisioned. For each block of patch code, an input on the OR gate and on the JMP target address generator is required. This scheme is inefficient because it provides for a fixed and limited number of patch code opportunities. A further inefficiency of the prior art scheme is that if the chip designers provide more patch code blocks, an increasingly large area of the silicon is required, therefore using valuable chip area that may be used for other circuitry. Also, as more comparators are operating on the chip, more power is required to drive them, which for battery-operated devices, is not desirable. Thus, in the past, there has been a trade off between providing a limited number of ROM code patch memory blocks with power conservation considerations, and silicon space considerations.
Therefore, a need exists for a method and apparatus of patching ROM code without the above-referenced limitations.